FIT awards Tech Grants to four promising start-ups from UNIL and EPFL

Four early-stage projects from UNIL and EPFL have each secured CHF 100,000 Tech Grants from the FIT to advance their technologies.

The Foundation for Innovation and Technology (FIT) has awarded four new Tech Grants, each worth CHF 100,000, to projects emerging from the University of Lausanne (UNIL) and the École Polytechnique Fédérale de Lausanne (EPFL). The grants will help the start-ups accelerate development, validate their technologies, and strengthen their market positioning.

Hevelion: spatial omics for new targeted therapies

Hevelion, stemming from UNIL’s Department of Computational Biology, is building an AI-powered platform to accelerate spatial biomarker discovery for complex diseases. By enabling researchers to analyze cellular interactions across large datasets, Hevelion aims to facilitate new diagnostics and targeted therapies. The start-up will use its grant to launch pilot projects with academic and pharmaceutical partners.

Kymansis: wearable cardiovascular monitoring

EPFL spin-off Kymansis is developing a wrist-worn, cuffless device to continuously monitor cardiovascular health. Using pressure sensors over the radial artery and advanced AI models, the device estimates blood pressure, arterial stiffness, and cardiac output with clinical-grade accuracy. The team will finalize design and begin clinical validation.

IRIS: accelerating biologics development

IRIS, a start-up from EPFL’s Laboratory of Systems Biology and Genetics, has created a platform combining imaging and molecular profiling to speed up biologics manufacturing. By predicting cell performance from morphology alone, the technology streamlines clone selection and process optimization. With FIT support, the team will validate the solution with industry partners.

Rhonexum: advancing cryogenic electronics

Rhonexum, based at EPFL’s Advanced Quantum Architecture Laboratory, is tackling the challenges of cryogenic circuit design. Its platform integrates automated measurement systems and transistor models to simulate and verify chips before fabrication. This approach reduces development costs and time by up to 90%. The funding will support further development and early user adoption.